<High Level Synthesis example : Quicksort engine(QSE)/TITLE> </HEAD> <BODY BGCOLOR="#000000" ALINK="#0066FF" LINK="#FFFF22" VLINK="#11FF66" TEXT="#DDCCFF"> <CENTER> <TABLE WIDTH=700> <TR><TD> <HR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=700> <TR><TD ALIGN=RIGHT> <H4><A HREF="./Works_03_NEC_R&D_J.html">Japanese</A> </TD></TR> </TABLE> </CENTER> <CENTER> <TABLE border=0 CELLSPACING=0 CELLPADDING=5> <TR> <TD ALIGN=CENTER><A HREF="./Works_02_NEC_V60_ICCD'86_E.html"><IMG SRC="./photo/previous.gif"></A></TD> <TD ALIGN=CENTER><A HREF="./index.html"><IMG SRC="/photo/top.gif"></A></TD> <TD ALIGN=CENTER><A HREF="./Works_04_Tokyo_Tech_E.html"><IMG SRC="/photo/next.gif"></A></TD> </TR> </TABLE> </CENTER> <H4> Hardware implementation of a software could be accomplished by Describing the algorithms in an appropriate hardware description language (HDL) <BR> <IMG SRC="NEC_QSE.jpg"><BR> <H4> Quicksort Eengine synthesized by describing the algorithm in an HDL designed by ryuichi TAKAHASHI in 1991<BR> <BR> Engine is the hardware implementing a function implemented originally by a software. <BR> <BR> <BR> <CENTER> <H4><FONT COLOR=BBDDFF> R & D Days of Ryuichi TAKAHASHI</FONT><BR> </CENTER> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD> <H4><FONT COLOR=FFCCEE> Ryuichi TAKAHASHI returned to the R & D unit of NEC on the April of 1989. </FONT><BR> </TD> </TR> </TABLE> </CENTER> <BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD ALIGN=CENTER><IMG SRC="./photo/RYUICHI_TAKAHASHI_1989_REG.jpg"> </TD> <TD ALIGN=CENTER><IMG SRC="./photo/NEC_R&D_1989_REG.jpg"> </TD> </TR> <TR> <TD> <H4><FONT COLOR=FFCCEE> 35 years old <A HREF="./Ryuichi_TAKAHASHI_1989.jpg">Ryuichi TAKAHASHI</A> in 1989. The car was the Z.</FONT> </TD> <TD> <H4><FONT COLOR=FFCCEE>R & D unit facility in Miyazakidai, Kanagawa. Ryuichi TAKAHASHI spent another 2 years here.</FONT> </TD> </TR> </TABLE> </CENTER> <BR> <HR WIDTH=80%> <BR> <BR> <BR> <CENTER> <H4><FONT COLOR=FFCCEE>A publication </FONT><BR> </CENTER> <BR> <BR> <DL> <DL> <DT><H4><FONT COLOR=00FFAA>1989-1991</FONT><BR> <BR> <BR> <DL> <DL> <DT><H4>A paper:<BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=500> <TR><TD ALIGN=LEFT> <OL><H4> <LI>Ryuichi TAKAHASHI and Takeshi YOSHIMURA:<BR> "Strategies for High Level Synthesis," (<FONT COLOR=CC6600>in Japanese</FONT>)<BR> The Trans. IEICE, VolJ74-A, No.2, pp.143-151 (1991)<BR> </OL> </TD></TR> </TABLE> </CENTER> </DL> </DL> </DL> </DL> <BR> <HR WIDTH=80%> <BR> <BR> <BR> <DL> <DL> <DT><H4><FONT COLOR=00FFAA>What is A^2DL?</FONT><BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD> <H4><FONT COLOR=EEDDFF> The letters A^2DL stand for An Automaton Description Language which is an original hardware description language developed in NEC by Ryuichi TAKAHASHI in 1980's.“Automaton description” means that the register transfer (RT) operations are listed in each state with the state transitions like the hardware description language DDL proposed by J. R. Duley and D. L. Dietmeyer in 1968. </FONT> </TD></TR> </TABLE> </CENTER> </DL> </DL> <BR> <BR> <DL> <DL> <DT><H4><FONT COLOR=00FFAA>What is A^2DL-DA</FONT><BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD> <H4><FONT COLOR=EEDDFF>A^2DL-DA was a high level design automation system which uses the A^2DL description as the input.<BR> </FONT> </TD></TR> </TABLE> </CENTER> </DL> </DL> <BR> <BR> <DL> <DL> <DT><FONT COLOR=00FFAA>A^2DL-DA had been used for what?</FONT><BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD> <H4><FONT COLOR=EEDDFF>We demonstrated a trial to convert a program into a semiconductor. Quicksort program written in A^2DL was fed into A^2DL-DA, which generated a specification of a chip named “Quicksort engine(QSE).”</FONT><BR> <BR> <BR> <CENTER> <TABLE BORDER=1 CELLSPACING=0 CELLPADDING=5 BGCOLOR=333344 WIDTH=500><H4> <TR><TD COLSPAN=2 ALIGN=CENTER BGCOLOR=333355><H4>Quicksort engine(QSE)</TD></TR> <TR><TD ALIGN=CENTER><H4>Process</TD><TD ALIGN=CENTER><H4>CMOS 1.5µm</TD></TR> <TR><TD ALIGN=CENTER><H4>Gate count</TD><TD ALIGN=CENTER><H4>2.6k</TD></TR> <TR><TD ALIGN=CENTER><H4>Clock speed</TD><TD ALIGN=CENTER><H4>10MHz</TD></TR> <TR><TD ALIGN=CENTER><H4>Power consumption</TD><TD ALIGN=CENTER><H4>280mW</TD></TR> </TABLE> </CENTER> <BR> <BR> <CENTER> <IMG SRC="./cgi/Works_03_NEC_R&D_E.cgi"> </CENTER> <BR> <BR> <H4> This could be regarded as one of the first trial to convert a program into semiconductor by writing the program in a hardware description language (HDL) to be fed into a synthesizer. <BR> Engine is the hardware implementing a function implemented By a software. Engine is very fast in comparison with the original corresponding software. In our trial engines were 10 times or 100 times faster than corresponding software. My boss Satoshi GOTO a fellow iEEEE used the word “software chip.” and asked “can it be done?” I thought it was a very good idea and said to him, “i” it’s a piece of cake.” Writing the function in hardware description language was my answere </TD></TR> </TABLE> </CENTER> </DL> </DL> <BR> <BR> <DL> <DL> <DT><H4><FONT COLOR=00FFAA>What is SSMD</FONT><BR> <BR> <CENTER> <TABLE BORDER=0 CELLSPACING=0 CELLPADDING=5 WIDTH=600> <TR><TD> <H4><FONT COLOR=EEDDFF> After returning to the university, Ryuichi TAKAHASHI tried to write automaton in Verilog HDL, which we call static state machine description (SSMD). SSMD is an automaton description like DDL in a sense that corresponding register transfer (RT) operations are listed in each state for a machine cycle with state transitions. Ryuichi TAKAHASHI used “‘define” statement for the state assignment. The same thing can be done by using “parameter” statement in Verilog HDL. We call “static” since there is no substitution to terminals unlike DDL. Hand shakings are expressed by appropriate combinational logic circuits statically. This feature was important to implement <A HREF="./computer/On_Demand_Simulation_E.html">a simulator</A>, which converts these circuits into functions in C language. These functions are called “on demand” by the main program in C language, which generated from the behavioral description as the automata.<BR> <BR> SSMD can be regarded as a behavioral description at register transfer level (RTL) in Verilog HDL. On the other hand, Verilog HDL description without using the automaton can be regarded as a structural description at the RTL, which can be written only after completing the RTL design, since the structural description requires all information for each register transfer operations for each register. When we write automaton, we only have to know the behaviors in each state. RTL specification is completed by writing down the automaton.<BR> <BR> Ryuichi TAKAHASHI used the SSMD in his class known as <A HREF="http://city-1.movie.coocan.jp/index.html" TARGET=_top>City-1</A>. </FONT> </TD></TR> </TABLE> </CENTER> </DL> </DL> <BR> <HR WIDTH=80%> <BR> <CENTER> <TABLE border=0 CELLSPACING=0 CELLPADDING=5> <TR> <TD ALIGN=CENTER><A HREF="./Works_02_NEC_V60_ICCD'86_E.html"><IMG SRC="./photo/previous.gif"></A></TD> <TD ALIGN=CENTER><A HREF="./index.html"><IMG SRC="/photo/top.gif"></A></TD> <TD ALIGN=CENTER><A HREF="./Works_04_Tokyo_Tech_E.html"><IMG SRC="/photo/next.gif"></A></TD> </TR> </TABLE> </CENTER> <BR> <HR> <BR> </TD> </TR> </TABLE> </CENTER> </BODY> </HTML>